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CWDM BIDI SFP Series

Eoptolink Technology Inc., Ltd. V2.d

Page 12 of 16

further details). Mod-Def 0 is grounded by the module to indicate that the module is present

Mod-Def 1 is the clock line of two wire serial interface for serial ID Mod-Def 2 is the data line of two

wire serial interface for serial ID

4) LOS (Loss of Signal) is an open collector/drain output, which should be pulled up with a 4.7K –

10KΩ resistor. Pull up voltage between 2.0V and VccT, R+0.3V. When high, this output indicates

the received optical power is below the worst-case receiver sensitivity (as defined by the standard

in use). Low indicates normal operation. In the low state, the output will be pulled to < 0.8V.

5) VeeR and VeeT may be internally connected within the SFP module.

6) RD-/+: These are the differential receiver outputs. They are AC coupled 100Ω differential lines

which should be terminated with 100Ω (differential) at the user SERDES. The AC coupling is done

inside the module and is thus not required on the host board. The voltage swing on these lines will

be between 370 and 2000 mV differential (185 –1000 mV single ended) when properly terminated.

7) VccR and VccT are the receiver and transmitter power supplies. They are defined as 3.3V ±5%

at the SFP connector pin. Maximum supply current is 300mA. Recommended host board power

supply filtering is shown below. Inductors with DC resistance of less than 1 ohm should be used in

order to maintain the required voltage at the SFP input pin with 3.3V supply voltage. When the

recommended supply-filtering network is used, hot plugging of the SFP transceiver module will

result in an inrush current of no more than 30mA greater than the steady state value. VccR and

VccT may be internally connected within the SFP transceiver module.

8) TD-/+: These are the differential transmitter inputs. They are AC-coupled, differential lines with

100Ω differential termination inside the module. The AC coupling is done inside the module and is

thus not required on the host board. The inputs will accept differential swings of 500 – 2400 mV

(250 – 1200mV single-ended), though it is recommended that values between 500 and 1200 mV

differential (250 – 600mV single-ended) be used for best EMI performance.

The serial interface uses the 2-wire serial CMOS EEPROM protocol defined for the ATMEL

AT24C02/04 family of components. When the serial protocol is activated, the host generates the

serial clock signal (SCL). The positive edge clocks data into those segments of the EEPROM that

are not write protected within the SFP transceiver. The negative edge clocks data from the SFP

transceiver. The serial data signal (SDA) is bi-directional for serial data transfer. The host uses

SDA in conjunction with SCL to mark the start and end of serial protocol activation. The memories

are organized as a series of 8-bit data words that can be addressed individually or sequentially.

The Module provides diagnostic information about the present operating conditions. The

transceiver generates this diagnostic data by digitization of internal analog signals. Calibration and

alarm/warning threshold data is written during device manufacture. Received power monitoring,

transmitted power monitoring, bias current monitoring, supply voltage monitoring and temperature

monitoring all are implemented. The diagnostic data are raw A/D values and must be converted to

real world units using calibration constants stored in EEPROM locations 56 – 95 at wire serial bus

address A2h. The digital diagnostic memory map specific data field define as following .For detail

EEPROM information, please refer to the related document of SFF 8472 Rev 9.3.

EEPROM

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